An Assessment of Integrated Digital Cellular

W ith the recent introduction of dual-core processors, the wide-scale transition to parallel processing may have finally begun. How will multicore processing evolve and what will be the dominant computer architecture of the future? As technology reaches the limits of CMOS and beyond, the physical realities of computing hardware may dictate the answer to these questions. The integration level for nanoscale electronic devices could eventually be in the range of 1010 to 1011 devices per square centimeter.1 At this level long interconnects represent a significant challenge to operation (energy consumption), design, and manufacturing (irregular arrays of interconnects with arbitrary connections). Also, nanoscale elements are likely to suffer from significantly higher failure rates than their contemporary counterparts. In addition, low-energy operation requirements and small transistor dimensions are likely to result in higher thermal and quantum error rates. Moreover, the problem of designing complex irregular structures at these density levels is becoming increasingly untenable. Given these realities, future nanoscale technology may drive a migration to different information processing and computing approaches. One such possibility is the class of digital cellular automata. The recent emergence of multicore architectures, driven by semiconductor technology constraints, motivates the investigation of cellular automata architectures as information processing alternatives. This possible migration to new computing architectures is theoretically predictable. Gianfranco Bilardi and Franco Preparata2 elegantly argued that, as computing technology approaches the physical limits of scaling (as dictated by the speed of light), ultimate device size reduction limits, and realizable fan-out and fan-in device constraints, it will naturally drive architectures of practical interest toward regular arrays of locally connected computational elements.